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I am interested in formal methods for the correct construction of hardware and software systems, with a focus on automated methods for checking compliance of an implementation with a specification. Techniques include model checking and automated testing.
I am particularly interested in applying these methods to practical hard- and software implementations given in languages like C/C++/Java, or HDLs such as Verilog and SystemC.
A full list of my papers is available here.
- Program Synthesis for Program Analysis
- Automated Formal Synthesis of Digital Controllers for State-Space Physical Plants
- Program Synthesis: Challenges and Opportunities
- A Widening Approach to Multi-Threaded Program Verification
- Lost in Abstraction: Monotonicity in Multi-Threaded Programs
- Don't sit on the fence: A static analysis approach to automatic fence insertion
- Ranking Function Synthesis for Bit-Vector Relations
- A Survey of Automated Techniques for Formal Software Verification
- A Tool for Checking ANSI-C Programs
- Predicate Abstraction of ANSI-C Programs using SAT
- 15-820A: Theorem Proving and Model Checking in PVS (Spring 2003)
- 17-651A: Models of Software Systems (Fall 2003)
- 251-0247-00 Formal Verification
- 251-0207-00 Seminar Digitaltechnik und Rechnerarchitektur
- 251-0211-00 Spezifikation und Verifikation objektorientierter Software
- 252-0014-00 Digitaltechnik
- 251-0276-00 Software Engineering Seminar
- Object Oriented Design
- Software Verification
- Computer-Aided Formal Verification
- Computer Architecture