Title: | Word Level Predicate Abstraction and Refinement for Verifying RTL Verilog |
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Links: | Homepage Document as PDF |
Authors: | Himanshu Jain |
Daniel Kroening EMail | |
Natasha Sharygina | |
Edmund Clarke EMail | |
Remarks: | |
Topics: |
Bibtex:
@article{jksc2007-tcad, AUTHOR = { Jain, Himanshu and Kroening, Daniel and Sharygina, Natasha and Clarke, Edmund }, TITLE = { Word Level Predicate Abstraction and Refinement for Verifying {RTL} {Verilog} }, YEAR = { 2008 }, PUBLISHER = { IEEE }, PAGES = { 366--379 }, JOURNAL = { IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) }, VOLUME = { 27 }, ISSUE = { 2 }, MONTH = { February }, }
We welcome feedback and comments at
kroening@cs.cmu.edu.
Last modified by Daniel Kröning.