Previous Contents Next

Appendix C   The DLX Instruction Set

This instruction set is taken from [MP95, MP98] with minimal modifications.

C.1   Instruction Formats



Figure C.1: Instruction formats of the DLX



C.2   Instruction Set Coding

IR[31:26] Mnemonic d Effect
Data Transfer, mem = M[RS1 + Sext(imm)]
100000 0x20 lb 1 RD = Sext(mem)
100001 0x21 lh 2 RD = Sext(mem)
100011 0x23 lw 4 RD = mem
100100 0x24 lbu 1 RD = 024mem
100101 0x25 lhu 2 RD = 016mem
101000 0x28 sb 1 mem = RD[7:0]
101001 0x29 sh 2 mem = RD[15:0]
101011 0x2b sw 4 mem = RD
Arithmetic, Logical Operation
001000 0x08 addi   RD = RS1 + Sext(imm)
001001 0x09 addiu   RD = RS1 + Sext(imm) (no overflow)
001010 0x10 subi   RD = RS1 - Sext(imm)
001011 0x11 subiu   RD = RS1 - Sext(imm) (no overflow)
001100 0x12 andi   RD = RS1 Ù Sext(imm)
001101 0x13 ori   RD = RS1 Ú Sext(imm)
001110 0x14 xori   RD = RS1 Å Sext(imm)
001111 0x15 lhgi   RD = imm016
Test Set Operation
011000 0x18 clri   RD = (false  ?  1  :  0)
011001 0x19 sgri   RD = (RS1 > Sext(imm)  ?  1  :  0)
011010 0x1a seqi   RD = (RS1 = Sext(imm)  ?  1  :  0)
011011 0x1b sgei   RD = (RS1 ³ Sext(imm)  ?  1  :  0)
011100 0x1c slsi   RD = (RS1 < Sext(imm)  ?  1  :  0)
011101 0x1d snei   RD = (RS1 ¹ Sext(imm)  ?  1  :  0)
011110 0x1e slei   RD = (RS1 £ Sext(imm)  ?  1  :  0)
011111 0x1f seti   RD = ( true  ?  1  :  0)
Control Operation
000100 0x04 beqz   PC = PC + 4 + (RS1 = 0  ?  Sext(imm) :  0)
000101 0x05 bnez   PC = PC + 4 + (RS1 ¹ 0  ?  Sext(imm) :  0)
000110 0x16 jr   PC = RS1
000111 0x17 jalr   R31 = PC + 4;   PC = RS1

Table C.1: I-type instruction layout

IR[31:26] IR[5:0] Mnemonic Effect
Shift Operation
000000 0x00 000000 0x00 slli RD = RS1 << SA
000000 0x00 000001 0x01 slai RD = RS1 << SA (arith.)
000000 0x00 000010 0x02 srli RD = RS1 >> SA
000000 0x00 000011 0x03 srai RD = RS1 >> SA (arith.)
000000 0x00 000100 0x04 sll RD = RS1 << RS2[4:0]
000000 0x00 000101 0x05 sla RD = RS1 << RS2[4:0] (arith.)
000000 0x00 000110 0x06 srl RD = RS1 >> RS2[4:0]
000000 0x00 000111 0x07 sra RD = RS1 >> RS2[4:0] (arith.)
Data Transfer
000000 0x00 010000 0x10 movs2i RD = SA
000000 0x00 010001 0x11 movi2s SA = RS1
Arithmetic, Logical Operation
000000 0x00 100000 0x20 add RD = RS1 + RS2
000000 0x00 100001 0x21 addu RD = RS1 + RS2 (no overflow)
000000 0x00 100010 0x22 sub RD = RS1 - RS2
000000 0x00 100011 0x23 subu RD = RS1 - RS2 (no overflow)
000000 0x00 100100 0x24 and RD = RS1 Ù RS2
000000 0x00 100101 0x25 or RD = RS1 Ú RS2
000000 0x00 100110 0x26 xor RD = RS1 Å RS2
000000 0x00 100111 0x27 lhg RD = RS2[15:0] 016
Test Set Operation
000000 0x00 101000 0x28 clr RD = ( false  ?  1  :  0)
000000 0x00 101001 0x29 sgr RD = (RS1 > RS2  ?  1  :  0)
000000 0x00 101010 0x2a seq RD = (RS1 = RS2  ?  1  :  0)
000000 0x00 101011 0x2b sge RD = (RS1 ³ RS2  ?  1  :  0)
000000 0x00 101100 0x2c sls RD = (RS1 < RS2  ?  1  :  0)
000000 0x00 101101 0x2d sne RD = (RS1 ¹ RS2  ?  1  :  0)
000000 0x00 101110 0x2e sle RD = (RS1 £ RS2  ?  1  :  0)
000000 0x00 101111 0x2f set RD = ( true  ?  1  :  0)

Table C.2: R-type instruction layout

IR[31:26] Mnemonic Effect
Control Operation
000010 0x02 j PC = PC + 4 + Sext(imm)
000011 0x03 jal R31 = PC + 4;   PC = PC + 4 + Sext(imm)
111110 0x3e trap trap = 1;   EPC = PC;   PC = SISR;
      ESR = SR;   ECA = masked CA;   SR = 0;
      EDATA = Sext(imm);
      clear CA but catch new interrupt events
111111 0x3f rfe SR = ESR;   PC = EPC

Table C.3: J-type instruction layout

IR[31:26] Mnemonic d Effect
Load, Store
110001 0x31 load.s 4 FD[31:0] = mem
110101 0x35 load.d 8 FD[63:0] = mem
111001 0x39 store.s 4 m = FD[31:0]
111101 0x3d store.d 8 m = FD[63:0]
Control Operation
000110 0x06 fbeqz   PC = PC + 4 + (FCC = 0  ?  Sext(imm) :  0)
000111 0x07 fbnez   PC = PC + 4 + (FCC ¹ 0  ?  Sext(imm) :  0)

Table C.4: FI-type instruction layout

IR[31:26] IR[5:0] Fmt Mnemonic Effect
Arithmetic and Compare Operations
010001 0x11 000000 0x00   fadd [.s, .d] FD = FS1 + FS2
010001 0x11 000001 0x01   fsub [.s, .d] FD = FS1 - FS2
010001 0x11 000010 0x02   fmul [.s, .d] FD = FS1 * FS2
010001 0x11 000011 0x03   fdiv [.s, .d] FD = FS1 / FS2
010001 0x11 000100 0x04   fneg [.s, .d] FD = - FS1
010001 0x11 000101 0x05   fabs [.s, .d] FD = abs(FS1)
010001 0x11 000110 0x06   fsqt [.s, .d] FD = sqrt(FS1)
010001 0x11 000111 0x07   frem [.s, .d] FD = rem(FS1, FS2)
010001 0x11 11c3 c2 c1 c0   fc.cond [.s, .d] FCC = (FS1 cond FS2)
Data Transfer
010001 0x11 001000 0x08 000 fmov.s FD[31:0] = FS1[31:0]
010001 0x11 001000 0x08 001 fmov.d FD[63:0] = FS1[63:0]
010001 0x11 001001 0x09   mf2i RS = FS1[31:0]
010001 0x11 001010 0x0a   mi2f FD[31:0] = RS
Conversion
010001 0x11 100000 0x20 001 cvt.s.d FD = cvt(FS1, s, d)
010001 0x11 100000 0x20 100 cvt.s.i FD = cvt(FS1, s, i)
010001 0x11 100001 0x21 000 cvt.d.s FD = cvt(FS1, d, s)
010001 0x11 100001 0x21 100 cvt.d.i FD = cvt(FS1, d, i)
010001 0x11 100100 0x24 000 cvt.i.s FD = cvt(FS1, i, s)
010001 0x11 100100 0x24 001 cvt.i.d FD = cvt(FS1, i, d)

Table C.5: FR-type instruction layout. Fmt=IR[8:6]

RM Symbol Rounding Mode
00 RZ toward zero
01 RNE to next even
10 RPI toward +¥
11 RMI toward -¥
Bit Symbol Purpose
0 OVF overflow
1 UNF underflow
2 INX inexact result
3 DBZ divide by zero
4 INV invalid operation

Table C.6: Coding of the rounding mode RM and the interrupt flags IEEEf

Previous Contents Next