Design and Evaluation of a RISC Processor with a Tomasulo Scheduler
Diplomarbeit
Lehrstuhl für Rechnerarchitektur
Prof. Wolfgang J. Paul
FB14 Informatik
Universität des Saarlandes
Daniel Kröning
Januar 1999
Introduction
Results
Outline
The Scheduling Algorithm
The DLX Architecture
The Tomasulo Scheduling Algorithm
The Reorder Buffer
The Overall Scheduling Protocol
Overall Scheduling Example
Tomasulo Hardware
Overview
The PC Environment
Instruction Memory Environment
Instruction Register Environment
Decode/Issue Environment
The Reservation Station Environments
Function Unit Environments
CDB Control Environment
Reorder Buffer Environment
Register File Environment
Memory System
Overview of the Data Memory System
The Data Memory Reservation Station
Dispatch Protocol
Implementation of the Dispatch Protocol
Memory Interface
Cost and Cycle Time
Hardware Cost
Cycle Time
Quality Survey and Comparison
Correctness
Data Consistency
Termination
Perspective
Auxiliary circuits
The Find First One Circuit
Conditional Sign Extension
The Integer Function Unit
ROB Auxiliary Circuits
Calculation of EPC/EPCn
The Cost and Delay Calculation Programs
The Hardware Cost Calculation Program
The Delay Calculation Program
The DLX Instruction Set
Instruction Formats
Instruction Set Coding
References